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ks57c01502/c01504/p01504 product overview 1 - 1 1 product overview the ks57c01502/c01504 single-chip cmos microcontroller has been designed for high-performance using samsung's newest 4 -bit cpu core, sam47 ( samsung arrangeable microcontrollers). the ks57p01504 is the microcontroller which has 4 kbyte one-time-programmable rom and the functions are the same to ks57c01502/c01504. with a four-channel comparator, eight led direct drive pins, serial i/o interface, and its ver satile 8-bit timer/counter, the ks57c01502/c01504 offers an excel lent design solution for a wide variety of general-purpose applica tions. up to 24 pins of the 30-pin sdip package can be dedicated to i/o. five vectored interrupts provide fast re sponse to internal and external events. in addition, the ks57c01502/c01504 's advanced cmos technol ogy provides for very low power consumption and a wide op erating voltage range ? all at a very low cost.
product overview ks57c01502/c01504/p 01504 1 - 2 features summary memory 512 4-bit data memory (ram) 2048 8-bit program memory (rom) :ks57c01502 4096 8-bit program memory (rom) :KS57C01504 24 i/o pins i/o: 18 pins, including 8 high current pins input only: 6 pins comparator 4-channel mode: internal reference (4-bit resolution) 16-step variable reference voltage 3-channel mode: external reference 150 mv resolution (worst case) 8-bit basic timer programmable interval timer watch-dog timer 8-bit timer/counter 0 programmable interval timer external event counter function timer/counter clock output to tclo0 pin watch timer time interval generation: 0.5 s, 3.9 ms at 4.19 m hz 4 frequency outputs to buz pin 8-bit serial i/o interface 8-bit transmit/receive mode 8-bit receive-only mode lsb-first or msb-first transmission selectable internal or external clock source bit sequential carrier supports 16-bit serial data transfer in arbitrary format interrupts two external interrupt vectors three internal interrupt vectors two quasi-interrupts memory-mapped i/o structure data memory bank 15 two power-down modes idle mode: only cpu clock stops stop mode: system clock stops oscillation sources crystal, ceramic for system clock crystal/ceramic: 0.4 - 6.0 mhz cpu clock divider circuit (by 4. 8, or 64) instruction execution times 0.95, 1.91, 15.3 s at 4.19 mhz 0. 67 , 1. 33 , 1 0.7 s at 6.0 mhz operating temperature ? 40 c to 85 c operating voltage range 1.8 v to 5.5 v package type 30 sdip , 32 sop
ks57c01502/c01504/p01504 product overview 1 - 3 function overview sam47 cpu all ks57-series microcontrollers have the advanced sam47 cpu core. the sam47 cpu can directly address up to 32 k bytes of program memory. the arithmetic logic unit (alu) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two cycles. cpu registers program counter a 11-bit program counter (pc) stores addresses for instruction fetch during program execution. usually, the pc is incremented by the number of bytes of the instruction being fetched. an exception is the 1-byte instruction ref which is used to reference instructions stored in a look-up table in the rom. whenever a reset operation or an interrupt occurs, bits pc1 1 through pc0 are set to the vector address. bit pc13?1 2 is reserved to support future expan sion of the device's rom size. stack pointer an 8-bit stack pointer (sp) stores addresses for stack operations. the stack area is located in the general-purpose data memory bank 0. the sp is read or written by 8-bit instructions and sp bit 0 must always be set to logic zero. during an interrupt or a subroutine call, the pc value and the program status word ( psw ) are saved to the stack area in ram. when the service routine has completed, the values referenced by the stack pointer are restored. then, the next instruc tion is exe cuted. the stack pointer can access the stack regardless of data memory access enable flag status. since the reset value of the stack pointer is not de fine d in firmware, it is recommended that the stack pointer be initialized to 00h by program code. this sets the first register of the stack area to data mem ory location 0ffh. program memory in its standard configuration, the 4096 8-bit rom is divided into three functional areas: ? 16-byte area for vector addresses ? 96-byte instruction reference area ? 1920-byte general purpose area (ks57c01502) ? 3968-byte general purpose area (KS57C01504) the vector address area is used mostly during reset operations and interrupts. these 16 bytes can also be used as general-purpose rom. the ref instruction references 2 1 -byte and 2 -byte instructions stored in locations 0020h?007fh. the ref instruction can also reference 3 -byte instructions such as jp or call. in order for ref to be able to reference these instructions, however, jp or call must be shortened to a 2-byte format. to do this, jp or call is written to the reference area with the format tjp or tcall instead of the normal instruction name. unused locations in the instruction reference area can be allocated to general-purpose use.
product overview ks57c01502/c01504/p 01504 1 - 4 data memory overview data memory is organized into three areas: ? 32 4-bit working registers ? 224 4 -bit general-purpose area in bank 0 ? 256 4 -bit general-purpose area in bank 1 ? 128 4-bit area in bank 15 for memory-mapped i/o addresses data stored in data memory can be manipulated by 1-, 4-, and 8-bit instructions. data memory is organized into two memory banks ? bank 0, bank 1 and bank 15. the select memory bank in- struction (smb) selects the bank to be used as work ing data memory. after power-on reset operation, initialization values for data memory must be redefined by code. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0 , 1 or 15. when the emb flag is logic zero, restricted area can be accessed. when the emb flag is set to logic one, all two data memory banks can be ac cessed ac cording to the current smb value. the emb = "0" addressing mode is used for nor mal program execution, whereas the emb = "1" mode is commonly used for interrupts, subroutines, mapped i/o, and repetitive access of specific ram addresses. working registers the ram's working register area in data memory bank 0 is further divided into four register banks. each register bank has eight 4-bit registers that are addressable either by 1-bit or 4 -bit instructions. paired 4-bit registers can be addressed as double registers by 8-bit instructions. register a is the 4-bit accumulator and double register ea is the 8-bit extended accumulator. double registers wx, wl, and hl are used as data pointers for indirect addressing. unused working reg isters can be used as general-purpose memory. to limit the possibility of data corruption due to in correct register bank addressing, register bank 0 is usually used for the main program and banks 1, 2, and 3 for interrupt service routines.
ks57c01502/c01504/p01504 product overview 1 - 5 control registers program status word the 8-bit program status word (psw) controls alu operations and instruction execution sequencing. it is also used to restore a program's execution environment when an interrupt has been serviced. program instructions can always address the psw regardless of the current value of data memory enable flags. before an interrupt or subroutine is processed, the psw values are pushed onto the stack in data memory bank 0. when the service routine is completed, the psw values are restored. is1 is0 emb erb c sc2 sc1 sc0 interrupt status flags (is1, is0), the enable memory bank and enable register bank flags (emb, erb), and the carry flag (c) are 1 - and 4-bit read/write or 8-bit read-only addressable. you can address the skip condition flags (sc0?sc2) using 8-bit read instructions only. select bank (sb) register two 4-bit registers store address values used to access specific memory and register banks: the select memory bank register, smb, and the select register bank reg ister, srb. 'smb n' instruction selects a data memory bank (0 or 15) and stores the upper four bits of the 12-bit data memory address in the smb register. to select register bank 0, 1, 2, or 3, and store the ad dress data in the srb, you can use the instruction 'srb n'. the instructions "push sb" and "pop sb" move srb and smb values to and from the stack for interrupts and subroutines. clock circuits system oscillation circuit generates the internal clock signals for the cpu and peripheral hardware. the system c lock can use a crystal, or ceramic oscillation source, or an externally-generated clock signal. to drive ks57c01502/c01504 using an external clock source, the external clock signal should be input to x in , and its inverted signal to x out . 4 -bit power control register controls the oscillation on/off, and select the cpu clock. the internal system clock signal ( fx) can be divided internally to produce three cpu clock frequencies ? fx/4, fx/8, or fx/64. interrupts interrupt requests may be generated internally by on-chip processes (intb, intt0, and ints) or externally by peripheral devices (int0 and int1). there are two quasi-interrupts: intk and intw. intk (ks0?ks2) detects falling edges of incoming signals and intw detects time intervals of 0.5 seconds or 3.91 milliseconds. the following components support interrupt processing: ? interrupt enable flags ? interrupt request flags ? interrupt priority registers ? power-down termination circuit
product overview ks57c01502/c01504/p 01504 1 - 6 power-down to reduce power consumption, there are two power-down modes: idle and stop. the idle instruction initiates idle mode; the stop instruction initiates stop mode. in idle mode, the cpu clock stops while peripher als continue to operate normally. in stop mode, system clock oscillation stops completely, halt s all operations except for a few basic peripheral functions. a power-down is terminated either by a or by an interrupt (with exception of the external interrupt int0). reset when is input during normal operation or during power-down mode, a reset operation is initi ated and the cpu enters idle mode. when the standard oscillation stabilization time in terval (31.3 ms at 4.1 9 mhz) has elapsed, normal cpu operation resumes. i/o ports the ks57c01502/c01504 has seven i/o ports. pin addresses for all i/o ports are mapped to locations ff0h? ff 6 h in bank 15 of the ram. there are 6 input pins and 18 configurable i/o pins including 8 high current i/o pins for a total of 24 i/o pins. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. timers and timer/counter the timer function has three main components: an 8-bit basic timer, an 8-bit timer/counter, and a watch timer. the 8-bit basic timer generates interrupt requests at precise intervals, based on the selected internal clock frequency. the programmable 8-bit timer/counter is used for counting events, modifying internal clock frequencies, and dividing external clock signals. the 8-bit timer/counter generates a clock signal ( ) for the serial i/o interface. the watch timer consists of an 8-bit watch timer mode register, a clock selector, and a frequency di vider circuit. its functions include real-time, watch-time measurement, and clock generation for fre quency output for buzzer sound. serial i/o interface the serial i/o interface supports the transmission or reception of 8 -bit serial data with an external device. the serial interface has the following functional components: ? 8-bit mode register ? clock selector circuit ? 8-bit buffer register ? 3-bit serial clock counter the serial i/o circuit can be set to transmit-and-re ceive, or to receive-only mode. msb-first or lsb-first transmission is also selectable. the serial interface can operate with an internal or an external clock source, or using the clock signal generated by the 8-bit timer/counter. transmission frequency can be modified by setting the appropriate bits in the sio mode register.
ks57c01502/c01504/p01504 product overview 1 - 7 bit sequential carrier the bit sequential carrier (bsc) is a 16-bit register that can be manipulated using 1-, 4-, and 8-bit instructions. using 1-bit indirect addressing, addresses and bit locations can be specified sequentially. in this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the l register. bsc data can also be manipulated using direct addressing. comparator the ks57c01502/c01504 contains a 4-channel comparator which can be multiplexed to normal input port. ? conversion time: 15.2 s, 121.6 s at 4.19 mhz ? two operation modes: three channels for analog input and one channel for external reference voltage input four channe ls for analog input and internal reference voltage level ? 16-level internal reference voltage generator ? 150 mv accuracy for input voltage level difference detection (maximum) ? comparator enable and disable the comparison results are read from the 4-bit cmpreg register after the specified conversion time.
product overview ks57c01502/c01504/p 01504 1 - 8 block diagram program status word flags arithmetic and logic unit instruction decoder internal interrupts reset interrupt control block stack pointer clock program memory ks57c01502: 2 kbyte KS57C01504: 4 kbyte 512 x 4-bit data memory input port 2 comparator p2.0/ ks0/cin0 p2.1/ks1/cin1 p2.2/ks2/cin2 p2.3/ks3/cin3 i/o port 5 p4.0 - p4.3 p6.0/ ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 i/o port 4 i/o port 6 x out x in program counter 8-bit timer/counter i/o port 3 i/o port 0 p0.0/ clo p0.1/tio p0.2/int1 p3.0/tcl0 p3.1/tclo0 p3.2/clo p5.0 - p5.3 serial i/o port input port 1 p0.0/ sck p0.1/so p0.2/si basic timer watch timer figure 1 -1 . ks57c01502/c01504 simplified block diagram
ks57c01502/c01504/p01504 product overview 1 - 9 pin assignments v ss xout xin test p1.0/int0 p1.1/int1 reset p0.0/ sck p0.1./so p0.2/si p2.0/cin0 p2.1/cin1 p2.2/cin2 p2.3/cin3 p3.0/tcl0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v dd p6.3/buz p6.2/ks2 p6.1/ ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 p3.2/clo p3.1/tclo0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ks57c01502 KS57C01504 (top view) 30-sdip v ss xout xin test p1.0/int0 p1.1/int1 reset nc p0.0/ sck p0.1./so p0.2/si p2.0/cin0 p2.1/cin1 p2.2/cin2 p2.3/cin3 p3.0/tcl0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd p6.3/buz p6.2/ks2 p6.1/ ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 nc p3.2/clo p3.1/tclo0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ks57c01502 KS57C01504 (top view) 32-sop figure 1 -2 . ks57c01502/c01504 pin assignment diagram
product overview ks57c01502/c01504/p 01504 1 - 10 pin descriptions table 1 -1 . ks57c01502/c01504 pin descriptions pin name pin type description number share pin p 0 .0 p 0 .1 p0.2 i/o 3-bit i/o port. 1-bit or 3-bit read/write and test are possible. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. pins are individually configurable as input or output. 8(9) 9(10) 10(11) so si p1.0 p1.1 i 2-bit input port. 1-bit or 2-bit read and test are possible. pull-up resistors are assignable by software. 5(5) 6(6) int0 int1 p2.0?p2.3 i 4-bit input port. 1-bit or 4-bit read and test are possible. 11-14 (12-15) cin0?cin3 p3.0 p3.1 p3.2 i/o same as port 0 15(16) 16(17) 17(18) tcl0 tclo0 clo p4.0?p4.3 p5.0?p5.3 i/o 4-bit i/o ports. 1-, 4-, or 8-bit read/write and test are possible. pins are individually configurable as input or output. 4-bit pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. the n-channel open-drain or push-pull output can be selected by software (1-bit unit) 18-21(20-23) 22-25(24-27) ? p6.0 p6.1 p6.2 p6.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test are possible. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. pins are individually configurable as input or output. 26(28) 27(29) 28(30) 29(31) ks0 ks1 ks2 buz int0 i external interrupts with detection of rising and falling edges 5(5) p1.0 int1 i external interrupts with detection of rising or falling edges 6(6) p1.1 cin0?cin3 i 4-channel comparator input. cin0?cin2: compara tor input only. cin3: comparator input or external reference input 11-14(12-15) p2.0?p2.3 i/o serial interface clock signal p0.0 so i/o serial data output 9(10) p0.1 si i/o serial data input 10(11) p0.2 tcl0 i/o external clock input for timer/counter 15(16) p3.0 tclo0 i/o timer/counter clock output 16(17) p3.1 clo i/o cpu clock output 17(18) p3.2 buz i/o 2 khz, 4 khz, 8 khz, or 16 khz frequency output at 4.19 mhz for buzzer sound 29(31) p6.3 note : pn numbers shown in parentheses '( )' are for 32-pin sop package; other pin numbers are for the 30-pin sdip.
ks57c01502/c01504/p01504 product overview 1 - 11 table 1 -1 . ks57c01502/c01504 pin descriptions (continued) pin name pin type description number share pin quasi-interrupt input with falling edge detection 26-28(28-30) p6.0?p6.2 v dd ? main power supply 30(32) ? v ss ? ground 1(1) ? i reset signal 7(7) ? test i test signal input (must be connected to v ss ) 4(4) ? x in , x out ? crystal or ceramic oscillator signal for system clock 3,2(3,2) ? note : pin numbers shown in parentheses '( )' are for 32-pin sop package; other pin numbers are for the 30-pin sdip. table 1 -2 . overview of ks57c01502/c01504 pin data sdip pin numbers pin names share pins i/o type reset value circuit type 1 v ss ? ? ? ? 2,3 xout , xin ? ? ? ? 4 test ? i ? ? 5,6 p1.0, p1.1 int0, int1 i input a-3 7 ? i ? b 8-10 p0.0 - p0.2 , so, si i/o input d-1 11-14 p2.0 - p2.3 cin0 - cin3 i input f-1 , f-2 (note) 15-17 p3.0 - p3.2 tcl0, tclo0, clo i/o input d-1 18-21 p4.0 - p4.3 ? i/o input e 22-25 p5.0 - p5.3 ? i/o input e 26 -29 p6.0 - p6.3 ks0, ks1, ks2, buz i/o input d-1 30 v dd ? ? ? ? note : i/o circuit type f-2 is implemented for p2.3 only.
product overview ks57c01502/c01504/p 01504 1 - 12 pin circuit diagrams v dd p - channel in n - channel figure 1 -3 . pin circuit type a p - channel resistor enable v dd pull-up resistor schmitt trigger in figure 1 -4 . pin circuit type a- 3 v dd pull-up resistor schmitt trigger in figure 1 -5 . pin circuit type b data output disable out v dd p - channel n - channel figure 1 -6 . pin circuit type c
ks57c01502/c01504/p01504 product overview 1 - 13 v dd pull-up resistor p - channel circuit type 4 resistor enable data output disable schmitt triger i/o figure 1 -7 . pin circuit type d-1 data output disable v dd p - channel pull-up resistor enable n - channel pne v dd pull-up resistor i/o figure 1 -8 . pin circuit type e digital input analog input figure 1 -9 . pin circuit type f-1 digital input analog input external v ref figure 1 - 1 0 . pin circuit type f-2
ks57c01502/c01504/p01504 electrical dat a 14- 1 14 electrical data table 14- 1. absolute maximum ratings (t a = 25 c ) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 5 ma all i/o ports active ? 15 output current low i ol ports 0, 3, and 6 5 ma ports 4 and 5 30 all ports, total + 100 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 14- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 ports 4 and 5 0.7v dd ? v dd v v ih2 ports 0, 1, 2, 3, 6, and 0.8v dd ? v dd v ih3 x in and x out v dd ? 0. 1 ? v dd input low voltage v il1 ports 4 and 5 ? ? 0.3v dd v v il2 ports 0, 1, 2, 3, 6, 0.2v dd v il3 x in and x out 0.1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 ma ports 0, 3, 4, 5, 6 v dd - 1.0 ? ? v
electrical data ks5 7c01502/c01504/p01504 14 - 2 table 14- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma ports 4, 5 ? ? 2 v v dd = 4.5v to 5.5 v i ol = 4.0ma all output pins except ports 4, 5 ? 2 input high leakage current i lih1 v in = v dd all input pins except x in and x out ? ? 3 m a i lih2 v in = v dd x in and x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out and ? ? ? 3 m a i lil2 v in = 0 v x in and x out ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v ? ? ? 3 m a pull-up resistor r l1 v i = 0 v; v dd = 5 v port 0, 1, 3, 4, 5, 6 25 50 100 k w v dd = 3 v 50 100 200 r l 2 v dd = 5 v ; v i = 0 v ; reset 100 250 400 v dd = 3 v 200 500 800
ks57c01502/c01504/p01504 electrical dat a 14- 3 table 14- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.0 8.0 ma current (1) crystal oscillator; c1=c2=22pf 4.19mhz 2.0 5.5 v dd = 3 v 10% 6.0mhz 1.3 4.0 4.19mhz 1.0 3.0 i dd 2 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 0.8 2.5 ma crystal oscillator; c1=c2=22pf 4.19mhz 0.6 1.8 v dd = 3 v 10% 6.0mhz 0.6 1.5 4.19mhz 0.4 1.0 i dd3 stop mode; v dd = 5.0 v 1 0% ? 0.5 3.0 m a stop mode; v dd = 3.0 v 1 0% 0.3 2.0 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include current drawn through internal pull-up resistor, output port drive currents and comparator. 2. the supply current assumes a cpu clock of fx/4. cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 1.05 mhz 15.625 khz cpu clock 4.2 mhz 6 mhz 400 khz main osc. freq. ( divided by 4 ) 1.5 mhz 1 2 2.7 3 4 5 6 7 figure 14- 1. standard operating voltage range
electrical data ks5 7c01502/c01504/p01504 14 - 4 table 14- 3. oscillators characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5 . 5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3.0 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3.0 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 4.2 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequ ency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
ks57c01502/c01504/p01504 electrical dat a 14- 5 table 14- 4. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf table 14- 5. comparator electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4.0 v to 5.5 v, v ss = 0 v) parameter symbol condition min typ max units input voltage range ? ? 0 ? v dd v reference voltage range v ref ? 0 ? v dd v input voltage accuracy v cin ? ? ? 150 mv input leakage current i cin, i ref ? ? 3 ? 3 m a table 14- 6. a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1 . 8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 m s v dd = 1.8 v to 5.5 v 0.95 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5 v 1 mhz tcl0 input high, low width t tih , t til v dd = 2.7 v to 5.5 v 0.48 ? ? m s v dd = 1.8 v to 5.5 v 1.8 cycle time t kcy v dd = 2.7 v to 5.5 v external source 800 ? ? ns internal source 670 v dd = 1.8 v to 5.5 v external source 3200 internal source 3800 table 14-6 . a.c. electrical characteristics ( concluded )
electrical data ks5 7c01502/c01504/p01504 14 - 6 (t a = ? 40 c to + 85 c, v dd = 1 . 8 v to 5.5 v) parameter symbol conditions min typ max units high, low width t kh , t kl v dd = 2 . 7 v to 5.5 v external source 335 ? ? ns internal source t kcy /2 ? 50 v dd = 1.8 v to 5.5 v external source 1600 internal source t kcy / 2 ? 150 si setup time to high t sik v dd = 2 . 7 v to 5.5 v external source 100 ? ? ns internal source 150 v dd = 1.8 v to 5.5 v external source 150 internal source 500 si hold time to high t ksi v dd = 2 . 7 v to 5.5 v external source 400 ? ? ns internal source 400 v dd = 1.8 v to 5.5 v external source 600 internal source 500 output delay for to so t kso (1) v dd = 2 . 7 v to 5.5 v external source ? ? 300 ns internal source 250 v dd = 1.8 v to 5.5 v external source 1000 internal source 1000 interrupt input high, low width t inth , t intl int0 ( 2) ? ? m s int1, ks0 ?ks2 10 input low width t rsl input 10 ? ? m s note s : 1. r (1 kohm) and c (100 pf) are the load resistance and load capacitance of the so output line. 2. minimum value for int0 is based on a clock of 2t cy or 128 / fx as assigned by the imod0 register setting.
ks57c01502/c01504/p01504 electrical dat a 14- 7 table 14-7 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait time (1) t wait released by ? 2 17 / fx ? ms released by interrupt ? (2) ? ms notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscilla tor start- up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu ins tructions during the wait time. timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode figure 14-2. stop mode release timing when initiated b y
electrical data ks5 7c01502/c01504/p01504 14 - 8 v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal operating mode power-down mode terminating signal (interrupt request) figure 14- 3. stop mode release timing when initiated by interrupt request measurement points 0.8 vdd 0.8 vdd 0.2 vdd 0.2 vdd figure 14- 4. a.c. timing measurement points (except for x in ) xin t xl t xh 1 / fx 0.2 v vdd - 0.2 v figure 14-5 . clock timing measurement at x in
ks57c01502/c01504/p01504 electrical dat a 14- 9 tcl t til t tih 1 / f ti 0.8 vdd 0.2 vdd figure 14- 6. tcl timing t rsl reset 0.2 v dd figure 14-7 . input timing for signal int0, 1 ks0 to ks2 t intl t inth 0.2 vdd 0.8 vdd figure 14- 8. input timing for external interrupts
electrical data ks5 7c01502/c01504/p01504 14 - 10 sck t kl t kh t cky 0.8 v dd input data output data 0.2 v dd 0.8 v dd 0.2 v dd si so t sik t ksi t kso figure 14-9 . serial data transfer timing
ks57c01502/c01504/p01504 mechanical data 15 - 1 15 mechanical data overview the ks57c01502/c01504/p01504 microcontroller is available in a 30 -pin sdip package ( samsung part number 30 - sdip - 400 ) and a 32 - sop package ( samsung part number 30 - sop - 450a ). note : dimensions are in millimeters. 27.88 max 27.48 0 .20 (1.30) 30-sdip-400 8.94 0 .20 #30 #1 0.56 0.10 1.12 0.10 3.81 0.20 5.21 max 1.778 0.51 min 3.30 0.30 #16 #15 0-15 0.25 + 0.10 - 0.05 10.16 figure 15 - 1. 30-sdip-400 package dimensions
mechanical data ks57c01502/c01504/p 01504 15 - 2 32-sop-450a 20.30 max 19.90 0 .20 #17 #16 0-8 0.25 + 0.10 - 0.05 11.43 8.34 0.20 0.90 0.20 0.05 min 2.00 0.10 2.20 max 0.10 max 1.27 note : dimensions are in millimeters. 12.00 0 .30 #32 #1 (0.43) 0.40 0.10 figure 15 -2 . 30-s o p-4 5 0 a package dimensions
ks57c01502/c01504/p01504 ks57p01504 otp 16- 1 16 ks57p01504 otp overview the ks57p01504 single-chip cmos microcontroller is the otp (one time programmable) version of the ks57c01502/c01504 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the ks57p01504 is fully compatible with the ks57c01502/c0504, both in function and in pin configuration. because of its simple programming requirements, the ks57p01504 is ideal for use as an evaluation chip for the ks57c01502/c01504. note: the bolds indicate an otp pin name. v ss /v ss xout xin v pp /test p1.0/int0 p1.1/int1 reset /reset p0.0/ sck p0.1./so p0.2/si p2.0/cin0 p2.1/cin1 p2.2/cin2 p2.3/cin3 p3.0/tcl0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v dd/ v dd p6.3/buz/ sclk p6.2/ks2/ sdat p6.1/ ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 p3.2/clo p3.1/tclo0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ks57p01504 (30-sdip) figure 16-1. ks57p01504 pin assignments (30-sdip package)
ks57p01504 otp ks57c01502/c01504/p 01504 16- 2 v ss /v ss xout xin v pp /test p1.0/int0 p1.1/int1 reset /reset nc p0.0/ sck p0.1./so p0.2/si p2.0/cin0 p2.1/cin1 p2.2/cin2 p2.3/cin3 p3.0/tcl0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd/ v dd p6.3/buz/ sclk p6.2/ks2/ sdat p6.1/ ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 nc p3.2/clo p3.1/tclo0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ks57p01504 (32-sop) note: the bolds indicate an otp pin name. figure 16-2. ks57p01504 pin assignments (32-sop package)
ks57c01502/c01504/p01504 ks57p01504 otp 16- 3 table 16-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p6.2 sdat 28 (30) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p6.3 sclk 29 (31) i/o serial clock pin. input only pin. test v pp (test) 4 (4) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 7 (7) i chip initialization v dd / v ss v dd / v ss 30/1 (32/1) i logic power supply pin. v dd should be tied to +5 v during programming. note: ( ) means the 32-sop otp pin number. table 16-2. comparison of ks57p01504 and ks57c01502/c01504 features characteristic ks57p01504 ks57c01502/c01504 program memory 4 k-byte eprom 2 k-byte mask rom: ks57c01502 4 k-byte mask rom: KS57C01504 operating voltage (v dd ) 2.0 v to 5.5 v 1.8 v to 5.5v otp programming mode v dd = 5 v, v pp (test)=12.5v ? pin configuration 30 sdip, 32 sop 30 sdip, 32 sop eprom programmability user program one time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the ks57p0504, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16?3 below. table 16-3. operating mode selection criteria v dd vpp (test) reg/ mem address (a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
ks57p01504 otp ks57c01502/c01504/p 01504 16- 4 otp electrical data table 16-4 . absolute maximum ratings (t a = 25 c ) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 5 ma all i/o ports active ? 15 output current low i ol ports 0, 3, and 6 5 ma ports 4 and 5 30 all ports, total + 100 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 16-5 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 ports 4 and 5 0.7v dd ? v dd v v ih2 ports 0, 1, 2, 3, 6, and 0.8v dd ? v dd v ih3 x in and x out v dd ? 0. 1 ? v dd input low voltage v il1 ports 4 and 5 ? ? 0.3v dd v v il2 ports 0, 1, 2, 3, 6, 0.2v dd v il3 x in and x out 0.1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 ma ports 0, 3, 4, 5, 6 v dd - 1.0 ? ? v
ks57c0502/c0504/p0504 microcontroller ks57p0504 otp 16? 5 table 16-5 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma ports 4, 5 ? ? 2 v v dd = 4.5 v to 5.5 v i ol = 4.0ma all output pins except ports 4, 5 ? 2 input high leakage current i lih1 v in = v dd all input pins except x in and x out ? ? 3 m a i lih2 v in = v dd x in and x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out and ? ? ? 3 m a i lil2 v in = 0 v x in and x out ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v ? ? ? 3 m a pull-up resistor r l1 v i = 0 v; v dd = 5 v port 0, 1, 3, 4, 5, 6 25 50 100 k w v dd = 3 v 50 100 200 r l 2 v dd = 5 v ; v i = 0 v ; reset 100 250 400 v dd = 3 v 200 500 800
ks57p01504 otp ks57c01502/c01504/p 01504 16? 6 table 16-5 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.0 8.0 ma current (1) crystal oscillator; c1=c2=22pf 4.19mhz 2.0 5.5 v dd = 3 v 10% 6.0mhz 1.3 4.0 4.19mhz 1.0 3.0 i dd 2 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 0.8 2.5 ma crystal oscillator; c1=c2=22pf 4.19mhz 0.6 1.8 v dd = 3 v 10% 6.0mhz 0.6 1.5 4.19mhz 0.4 1.0 i dd3 stop mode; v dd = 5.0 v 1 0% ? 0.5 3.0 m a stop mode; v dd = 3.0 v 1 0% 0.3 2.0 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include current drawn through internal pull-up registers, output port drive currents and comparator. 2. the supply current assumes a cpu clock of fx/4. cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 1.05 mhz 15.625 khz cpu clock 4.2 mhz 6 mhz 400 khz main osc. freq. ( divided by 4 ) 1.5 mhz 1 2 2.7 3 4 5 6 7 figure 16-3 . standard operating voltage range
ks57c0502/c0504/p0504 microcontroller ks57p0504 otp 16? 7 table 16-6 . oscillators characteristics (t a = ? 40 c + 85 c, v dd = 2.0 v to 5 . 5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3.0 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3.0 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillatin g stabilization after a power-on occurs, or when stop mode is terminated.
ks57p01504 otp ks57c01502/c01504/p 01504 16? 8 table 16-7 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf table 16-8 . comparator electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4.0 v to 5.5 v, v ss = 0 v) parameter symbol condition min typ max units input voltage range ? ? 0 ? v dd v reference voltage range v ref ? 0 ? v dd v input voltage accuracy v cin ? ? ? 150 mv input leakage current i cin, i ref ? ? 3 ? 3 m a table 16-9 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 m s v dd = 2.0 v to 5.5 v 0.95 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 2.0 v to 5.5 v 1 mhz tcl0 input high, low width t tih , t til v dd = 2.7 v to 5.5 v 0.48 ? ? m s v dd = 2.0 v to 5.5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? ns internal sck source 670 v dd = 2.0 v to 5.5 v external sck source 3200 internal sck source 3800
ks57c0502/c0504/p0504 microcontroller ks57p0504 otp 16? 9 table 16-9 . a.c. electrical characteristics ( concluded ) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units sck high, low width t kh , t kl v dd = 2 . 7 v to 5.5 v external sck source 335 ? ? ns internal sck source t kcy /2 - 50 v dd = 2.0 v to 5.5 v external sck source 1600 internal sck source t kcy / 2 - 150 si setup time to sck high t sik v dd = 2 . 7 v to 5.5 v external sck source 100 ? ? ns internal sck source 150 v dd = 2.0 v to 5.5 v external sck source 150 internal sck source 500 si hold time to sck high t ksi v dd = 2 . 7 v to 5.5 v external sck source 400 ? ? ns internal sck source 400 v dd = 2.0 v to 5.5 v external sck source 600 internal sck source 500 output delay for sck to so t kso (1) v dd = 2 . 7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 2.0 v to 5.5 v external sck source 1000 internal sck source 1000 interrupt input high, low width t inth , t intl int0 ( 2) ? ? m s int1, ks0 ?ks2 10 reset input low width t rsl input 10 ? ? m s note s : 1. r(1kohm) and c (100pf) are the load resistance and load capacitance of the so output line. 2. minimum value for int0 is based on a clock of 2t cy or 128 / fx as assigned by the imod0 register setting.
ks57p01504 otp ks57c01502/c01504/p 01504 16? 10 table 16-10 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.0 ? 5.5 v data retention supply current i dddr v dddr = 2.0 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? ms notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu ins tructions during the wait time.
ks57c0502/c0504/p0504 microcontroller ks57p0504 otp 16? 11 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 16-4. otp programming algorithm

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